High speed data processing machines typically include a high speed cache or buffer that stores lines of data that are available for quick access during processing. The lines of data are associated with error checking and correcting codes in order to detect and/or correct errors before data from the cache is utilized by the processing machine.
A high speed cache typically organizes data in sections such as lines for addressing and error checking and correcting (ECC) purposes.
A processing unit in the data processing machine may update only a portion of the line, such as a byte or a word. A problem arises in recomputing the ECC code for the line subject of the partial update. In the prior art, in order to update the ECC code after a partial update, the ECC code for the line prior to the update and at least a portion of the line itself prior to the update is read. This information is then utilized to generate an updated ECC code to be stored with the line after the update.
The system described in the above cross-referenced U.S. patent application entitled CACHE ERROR CODE UPDATE, rather than reading the ECC code for the line prior to the update, reads only the portion of the line that is not being updated during a given write. Based on that portion of the line, a partial ECC code is generated which is combined with an ECC code generated from the update to create a new ECC code for the entire line.
In the prior art and the CACHE ERROR CODE UPDATE schemes, the generation of an accurate ECC code for a line after an update is dependent upon the line in the cache prior to the update. If the line in the cache prior to the update includes an error, the problem of calculating an accurate ECC code for the line after the update is complicated.